Arithmetic Logic Unit (ALU)

The ALU executes all arithmetic and logical operations defined by the ISA:

Arithmetic: add, sub, mul, div
Logical: and, or, xor, shifts (sll, srl)
Comparisons: Used in branch instructions like beq, bne, blt, bge

Overflow Detection

Overflow occurs when the result of an operation cannot be represented within the fixed bit-width (e.g., 64 bits).
In RISC-V, overflow in signed operations (e.g., add, addi, sub) triggers a hardware exception, and the Exception Program Counter (EPC) stores the address of the faulting instruction.

Multiplication

Implemented via shifts and adds (binary long multiplication).
RISC-V provides multiple multiply instructions:
- mul: lower 64 bits of the product
- mulh: upper 64 bits (both operands signed)
- mulhu: upper bits (both unsigned)
- mulhsu: one signed, one unsigned
Overflow check: If mulh ≠ 0 (for positive operands), 64-bit overflow likely occurred.

Division

Implemented via repeated subtraction and left shifts.
Instructions:
- div, rem: signed division and remainder
- divu, remu: unsigned versions
No exceptions are raised for:
- Division by zero → returns a defined (but meaningless) value
- Overflow → software must validate results

Floating-Point Arithmetic (IEEE 754 Standard)

$$
(−1)
^{\text{sign}}
\times 2^{\text{Exponent}−\text{Bias}}
\times(1+\text{Fraction})
$$

Formats

Precision	Sign	Exponent	Fraction	Bias
Single	1	8	23	127
Double	1	11	52	1023

Hidden bit: The leading ‘1’ in normalized numbers is implicit (not stored), increasing precision.
Special values:
- ±0: exponent = 0, fraction = 0
- Denormalized: exponent = 0, fraction ≠ 0 (for gradual underflow)
- ±∞: exponent = all 1s, fraction = 0
- NaN: exponent = all 1s, fraction ≠ 0 (e.g., result of 0/0)

IEEE 754-2008 contains a half precision that is only 16 bits wide. The left most bit is still the sign bit, the exponent is 5 bits wide and has a bias of 15, and the mantissa is 10 bits long. A hidden 1 is assumed.

Write down the bit pattern to represent $-1.5625\times 10^{-1}$ assuming a version of this format, which uses an excess-16 format to store the exponent. Comment on how the range and accuracy of this 16-bit floating point format compares to the single precision IEEE 754 standard.

指数部分：5bit
尾数部分：10bit
偏移量：16

十进制小数转换为二进制小数（不计符号）

$$
(0.15625){10}=(0.00101){2}=(101)_2\times 2^{-3}
$$

符号位：1
指数部分：真实指数为 $-3$，加上偏移量 16，为 $(13)_{10}=(0\ 1101)_2$
尾数部分：隐去最高位 1，右侧补零：$(0100\ 0000\ 00)_2$

拼接：符号位+指数部分+尾数部分

$$
(1011\ 0101\ 0000\ 0000)2=(B500){16}
$$

Addition/Subtraction

Restore hidden bits in both operands.
Align exponents by shifting the smaller operand’s fraction right.
Add/subtract fractions.
Normalize result (adjust exponent so $fraction \in [1, 2)$).
Round using Guard (G), Round (R), and Sticky (S) bits.
Re-hide the leading 1 before storing.

Calculate the sum of $2.6125\times 10^1$ and $4.150390625\times10^{-1}$ by hand, assuming A and B are stored in the 16-bit half precision described in Question below. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps.

Convert A and B to float number:

分别将整数和小数转为二进制：

	整数	小数
A	$(26)_{10}=(1\ 1010)_2$	$(0.125)_{10}=(0.001)_2$
B	$(0)_{10}=(0)_2$	$(0.4150390625)_{10}=(0.0110\ 1010\ 0100)$

移动浮点，获得尾数和指数

	尾数	指数
A	$1010\ 0010\ 00$	4
B	$1010\ 1001\ 00$	-2

对齐指数，将较小指数右移，得 B 尾数为 $0000\ 0010\ 10$，指数为 4

同时有 Guard、Round、Sticky 保留，附在 B 尾数末尾：$0000\ 0010\ 10\ 101$

Guard（靠近尾部第一个数）：1
Round（靠近尾部第二个数）：0
Sticky（靠近尾部第三个数之后所有位的 OR）：1

满足以下任一条件时，需要进位：

G = 1 且 (R = 1 或 S = 1)
→ 表示被舍去的部分大于 0.5 个最低有效位（ULP），应向上舍入。
G = 1 且 R = 0 且 S = 0
→ 表示被舍去的部分 正好等于 0.5 ULP（即“中间值”）。此时采用 “舍入到偶数” 规则：
- 如果保留部分的最低有效位（LSB）为 1（即奇数），则进位使其变为偶数；
- 如果 LSB 为 0（已是偶数），则不进位。

尾数相加：$1010\ 0010\ 00+0000\ 0010\ 10\ 101=1010\ 1000\ 10\ 101=1010\ 1000\ 11$

最后结果为（需要加上尾数省略的 1）：

$$
(1.1010\ 1000\ 11)2\times 2^{4}=(11010.1000\ 11)2=(26){10}+(0.546875){10}=(26.546875)_{10}
$$

Multiplication

Add biased exponents and subtract bias.
Multiply fractions → double-width result.
Normalize (may require 1-bit right shift).
Round and re-hide leading bit.